File:CPU block diagram.svg

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Original file ‎(SVG file, nominally 260 × 360 pixels, file size: 10 KB)

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Description
English: Block diagram of a hypothetical simple CPU, showing instruction fetch, decode, data registers, ALU, and memory interface, and major relationships.
Español: Diagrama de una hipotética y simple "Unidad Central de Proceso" (CPU), mostrando la captura de una instrucción y su decodificación, así como los registros de datos, la "Unidad Aritmético-Lógica" (ALU), la interfaz de memoria, y otras relaciones.
Italiano: Diagramma a blocchi semplificato di una CPU, dall'alto: il ricevitore di istruzioni, il decodificatore, i registri dati, l'unità aritmetico-logica (ALU); a destra è rappresentata l'interfaccia alla memoria.
Date 1 June 2006 (original upload date)
Source Own work based on: CPU block diagram.png
Author
SVG development
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Licensing[edit]

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GNU head Permission is granted to copy, distribute and/or modify this document under the terms of the GNU Free Documentation License, Version 1.2 or any later version published by the Free Software Foundation; with no Invariant Sections, no Front-Cover Texts, and no Back-Cover Texts. A copy of the license is included in the section entitled GNU Free Documentation License. Subject to disclaimers.

Original upload log[edit]

The original description page was here. All following user names refer to en.wikipedia.
  • 2007-04-12 03:48 R. S. Shaw 260×360× (10716 bytes) Revision removing rounded corners from ALU
  • 2006-06-01 03:52 Booyabazooka 260×360× (12541 bytes) :''This vector image was converted from the original raster version: [[:Image:CPU block diagram.png]]'' ==Summary== Block diagram of a hypothetical simple CPU, showing instruction fetch, decode, data registers, ALU, and memory interface, and major relati

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Date/TimeThumbnailDimensionsUserComment
current14:32, 13 October 2012Thumbnail for version as of 14:32, 13 October 2012260 × 360 (10 KB)OgreBot (talk | contribs)(BOT): Uploading old version of file from en.wikipedia; originally uploaded on 2007-04-12 03:48:00 by R. S. Shaw
12:47, 12 November 2006Thumbnail for version as of 12:47, 12 November 2006260 × 360 (12 KB)German (talk | contribs){{Information |Description=Block diagram of a hypothetical simple CPU, showing instruction fetch, decode, data registers, ALU, and memory interface, and major relationships. |Source=http://en.wikipedia.org/wiki/Image:CPU_block_diagram.svg |Date=2006-06-01

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